1. Field of the Invention
The present invention relates to an information processing apparatus, a process control method and a computer program, and it particularly relates to an information processing apparatus, a process control method and a computer program by which to improve accessibility to a resource for logical processors in a structure where various data processings are carried out in a manner that a plurality of logical processors share the resources available in the information processing apparatus.
2. Description of the Related Art
In a multi-OS system having a plurality of operating systems (OSs) running within the single system, different processes can be executed by the respective OSs, in which processings are done by switching time-sequentially the use of hardware, such a CPU, a memory and the like, common to the system.
Scheduling of processes (tasks) to be executed respectively by a plurality of OSs is carried out, for instance, by partition management software. For example, if there are two operating systems, OS(α) and OS(β), coexisting in a system and a process of OS(α) is set as a partition A and a process of OS(β) as a partition B, then the partition management software determines an execution schedule of the partition A and the partition B and executes the processes of the OSs by assigning hardware resources according to the determined schedule.
A known technology concerning task management in a multi-OS system is introduced by Reference (1) in the following Related Art List. Reference (1) discloses a task scheduling technique for preferentially executing processes with higher emergency In task management carried out at each of a plurality of OSs.
As mentioned above, subjects of various data processings are set as partitions. More specifically, logical partitions are set as subjects that receive allocation of resources within the system, and various resources, including usable time for physical processor units, virtual address space and memory space, are allocated to the logical partitions so that the processes using the allocated resources may be executed. For each of the logical partitions, a logical processor corresponding to any of physical processors is set, and a data processing according to the logical processor is carried out. It is to be noted that there is not always a one-to-one correspondence between logical processors and physical processors; there may be cases where a plurality of physical processors are associated with a single logical processor or where a single physical processor is associated with a plurality of logical processors.
When a plurality of processings using logical processors are executed in parallel, the physical processors are used by the plurality of logical processors according to a scheduling. That is, the plurality of logical processors use the physical processors by time sharing.
Now let us consider a system comprising a main processor and a plurality of sub-processors.
For example, let us consider an access processing when a single logical sub-processor is allocated to a single physical sub-processor as shown in FIG. 1, or, in particular, an access processing to a logical sub-processor A when the logical sub-processor A uses the physical sub-processor 1 exclusively and the logical sub-processor B uses the physical sub-processor 2 exclusively.
For instance, let us assume that an OS associated with a logical partition to which a logical sub-processor A has been set tries to access the logical sub-processor A. The MMIO (Memory-Napped I/O) register information, local storage area and the like held by a physical processor 1 occupied by the logical sub-processor A are mapped to an address space of a logical partition associated with the logical sub-processor A. The area thus mapped is associated with the exclusively used physical sub-processor 1. Therefore the OS associated with the logical partition can always access the logical sub-processor A. By gaining access to the logical sub-processor A, it is possible to obtain various information, such as local storage information, corresponding to the logical sub-processor A.
Note that the MMIO (Memory-Mapped I/O) is an input/output control mechanism for controlling hardware by memory mapping, which accomplishes hardware control by write processing or read processing using specific memory positions.
On the other hand, let us suppose, for instance, that processings are executed by time sharing with a plurality of logical sub-processors allocated to a single physical sub-processor as shown in FIG. 2. Then, at the timing when a logical sub-processor A is using a physical sub-processor 1 as with access A in FIG. 2, the OS associated with the logical partition can access the logical sub-processor A in the same-way as the aforementioned processing. However, at the timing when a logical sub-processor A is not using a physical sub-processor 1 as with access B in FIG. 2, it is not possible to execute an access to the logical sub-processor A because, at this timing, the logical sub-processor A is not using any physical sub-processor and thus the MMIO (Memory-Mapped I/O) register information, local storage area, and the like for a physical sub-processor are not mapped in an address space of a logical partition associated with the logical sub-processor A. In this case, it is necessitated that the logical sub-processor A remains on standby until the time comes to use a physical sub-processor by time sharing, thus resulting in a problem of delayed data processing.
Related Art List
(1) Japanese Patent Application Laid-Open No. 2003-345612.